The present invention relates to a address decoding system for a microcontroller system and, more particularly, to an address decoding system particularly suited for postage metering applications.
In electronic postage metering machines, and like devices, it is customary to develop a specific microcontroller system for each model of postage meters to accommodate the unique control requirements of each meter model. Conventionally, a microcontroller system, of the type customarily used in postage metering applications, is comprised of a programmable microprocessor in bus communication with a read-only memory (ROM) or program memory, random access memory (RAM), non-volatile memories (NVMs) and an application specific integrated circuit (ASIC). Conventionally, the ASIC chip generates the chip select signals and write enable signal in order to write to the NVMs pursuant to address instructions from the microprocessor. One of the factors which have predicated customization of the ASIC is that the microprocessor bus cycle is matched to the write time required by the nonvolatile memories.